Exemplary embodiments relate to a memory system and a method of operating the same and, more particularly, to a memory system including a nonvolatile memory device and a method of operating the same.
In a nonvolatile memory device such as a NAND flash memory device, data stored in memory cells may be classified based on levels in which threshold voltages of the memory cells are distributed. For example, when storing 2-bit data in one memory cell, threshold voltages of the memory cells may be distributed on the basis of 4 (22) different levels. Furthermore, when storing 1-bit data in one memory cell, threshold voltages of the memory cells may be distributed into 2 (21) levels.
The memory cell array of the NAND flash memory device includes a plurality of memory blocks. While 1-bit data is stored in some of the memory blocks in order to increase the operating speed, 2-bit data may be stored in the remaining memory blocks in order to increase the data storage capacity. In the case where 1-bit data is stored in one memory cell, only one kind of program operation for raising the threshold voltages of selected memory cells based on data to be stored in the memory cells is to be performed. In order to store 2-bit data in one memory cell, however, a least significant bit (hereinafter referred to as an ‘LSB’) program operation for storing LSB data and a most significant bit (hereinafter referred to as an ‘MSB’) program operation for storing MSB data are to be performed. Threshold voltage distributions of memory cells differ for each case (i.e., when 1-bit data is stored and when 2-bit data is stored).
FIG. 1 is a diagram illustrating threshold voltage distributions of memory cells.
Referring to FIG. 1, in the case where 1-bit data is stored in a memory cell, only an LSB program operation may be performed without a MSB program operation. At this time, MSB data of the memory cell is set to ‘1’ in order for the operation of the memory cell to match with the operation of another memory cell in which the MSB data is stored. Accordingly, through the program operation, only the 1-bit data may be stored in the memory cell as LSB data. Since only the 1-bit data is stored in the memory cell, threshold voltages of such memory cells are divided into a level (that is, an erase level) lower than 0 V and a level higher than 0 V. Furthermore, levels of the threshold voltages are determined based on the LSB data (1, 0) of one stored bit.
Meanwhile, in the case where 2-bit data is stored in a memory cell, an LSB program operation and an MSB program operation are sequentially performed. That is, 2-bit data, including LSB data and MSB data, is stored in one memory cell. Since the 2-bit data is stored in the memory cell, threshold voltages of such memory cells are classified into a level (that is, an erase level) lower than 0 V and first to third program levels higher than 0 V. Furthermore, levels of the threshold voltages are determined based on the data of stored 2 bits (11, 01, 00, and 10).
In the case where only 1-bit data is stored in a memory cell, it does not matter if a threshold voltage distribution is wide, because there is only one threshold voltage distribution higher than 0 V. However, in the case where 2-bit data is stored in a memory cell, a threshold voltage distribution is to be narrow because there are three threshold voltage distributions higher than 0 V.
Furthermore, when an LSB data read operation is performed, a read voltage R1 or R2, which is supplied to a selected word line in order to output the LSB data stored in the memory cells, is to be differently set based on the number of bits of data stored in the memory cells. The details thereof are described as follows.
FIGS. 2A and 2B are diagrams illustrating a method of operating a semiconductor memory device.
Referring to FIGS. 1 and 2A, at step S212, a first read voltage R1 is supplied to a selected word line in order to output LSB data stored in memory cells. Not only the memory cells for storing the data, but also a flag cell for storing state information about the memory cells is coupled to the selected word line. For example, information about whether an MSB program operation for the memory cells has been performed is stored in the flag cell. In general, if data ‘1’ is stored in the flag cell and threshold voltages of the memory cells are lower than 0 V, it means that the MSB program operation has not been performed and only 1-bit data is stored in the memory cells. If data ‘0’ is stored in the flag cell and threshold voltages of the memory cells are higher than 0 V, it means that the MSB program operation has been performed and 2-bit data is stored in the memory cells. When the first read voltage R1 is supplied to the selected word line, data stored in the memory cells and data stored in the flag cell are outputted at the same time.
At step S214, it is determined whether the MSB program operation for the memory cells has been performed based on the data stored in the flag cell.
If, as a result of the determination, the data ‘1’ is stored in the flag cell, the MSB program operation for the memory cells is determined not to have been performed. In this case, since 1-bit data is stored in each of the memory cells, the data stored in the memory cells can be classified into ‘1’ and ‘0’ using the first read voltage R1 as in FIG. 1. The data outputted from the memory cells is externally outputted.
If, as a result of the determination, the data ‘0’ is stored in the flag cell, the MSB program operation for the memory cells is determined to have been performed. In this case, LSB data stored in the memory cells cannot be classified into ‘1’ and ‘0’ using the first read voltage R1. Accordingly, at step S216, the data stored in the memory cells is outputted by supplying the second read voltage R2 to the selected word line. If threshold voltages of the memory cells are lower than the second read voltage R2, data ‘1’ is outputted, and if threshold voltages of the memory cells are higher than the second read voltage R2, data ‘0’ is outputted
FIG. 2B shows an example in which the second read voltage R2 is supplied earlier than the first read voltage R1. If the second read voltage R2 is first supplied, LSB data of memory cells on which an MSB program operation has not been performed cannot be accurately outputted. For this reason, the data stored in the memory cells is to be outputted by supplying the first read voltage R1 to the selected word line at step S226.
As described above, both the first and the second read voltages may be used in order to output LSB data based on the number of bits of data stored in memory cells or whether an MSB program operation has been performed. In this case, the operating speed may be lowered.